In some tile rendering architectures, there is a 1:1 mapping between the visibility bins or regions and the render tiles. This 1:1 mapping could encounter problems when the number of render tiles exceeds the number of visibility bins that the Graphical Processing Unit (GPU) could generate in parallel. This is because multiple visibility passes are needed and it causes non-graceful degradation in performance.
For example, FIG. 11 illustrates a prior-art visibility bin scheme. The visibility bins 1106 and 1108 are mapped 1:1 to the render tiles 1114 and 1116 respectively after performing the tile render pass stages 1110 and 1112. When the number of render tiles exceeds the number of visibility bins under the prior-art visibility bin scheme, multiple visibility passes 1104 over (possibly hierarchical) subsets of the render tiles have to be performed for the scene objects 1102. This causes the non-graceful degradation in performance.